2 search results - page 1 / 1 » Unified Challenges in Nano-CMOS High-Level Synthesis |
137
Voted
VLSID
2009
IEEE
16 years 4 months ago
2009
IEEE
: The challenges in nano-CMOS circuit design include the following: variability, leakage, power, thermals, reliability, and yield. This talk will focus on interdependent considerat...
159
Voted
FDL
2007
IEEE
15 years 10 months ago
2007
IEEE
SystemVerilog encapsulates both design description and verification properties in one language and provides a unified environment for engineers who have the formidable challenge o...