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FMCAD
2000
Springer
15 years 3 months ago
Model Checking Synchronous Timing Diagrams
Abstract. Model checking is an automated approach to the formal verification of hardware and software. To allow model checking tools to be used by the hardware or software designer...
Nina Amla, E. Allen Emerson, Robert P. Kurshan, Ke...
82
Voted
AICCSA
2006
IEEE
179views Hardware» more  AICCSA 2006»
15 years 5 months ago
Supporting the SPEM with a UML Extended Workflow Metamodel
The specification, analysis, and administration of business processes have charged great importance in this last time. This has been caused by a competitive industry necessity, dy...
Narayan C. Debnath, Daniel Riesco, Manuel Pé...
VMCAI
2010
Springer
15 years 9 months ago
Temporal Reasoning for Procedural Programs
While temporal verification of programs is a topic with a long history, its traditional basis--semantics based on word languages--is illsuited for modular reasoning about procedura...
Rajeev Alur, Swarat Chaudhuri
106
Voted
ARCS
2006
Springer
15 years 3 months ago
Fault-Tolerant Time-Triggered Ethernet Configuration with Star Topology
: We have shown in our past work that the standard configuration of Time-Triggered (TT) Ethernet unifies real-time and non-real-time traffic within a single coherent communication ...
Astrit Ademaj, Hermann Kopetz, Petr Grillinger, Kl...
PPOPP
2009
ACM
16 years 6 days ago
A comprehensive strategy for contention management in software transactional memory
In Software Transactional Memory (STM), contention management refers to the mechanisms used to ensure forward progress-to avoid livelock and starvation, and to promote throughput ...
Michael F. Spear, Luke Dalessandro, Virendra J. Ma...