Sciweavers

1631 search results - page 143 / 327
» Uniform Distributed Synthesis
Sort
View
ISQED
2010
IEEE
227views Hardware» more  ISQED 2010»
15 years 10 months ago
Post-synthesis sleep transistor insertion for leakage power optimization in clock tree networks
Leakage power has grown significantly and is a major challenge in SoC design. Among SoC's components, clock distribution network power accounts for a large portion of chip po...
Houman Homayoun, Shahin Golshan, Eli Bozorgzadeh, ...
BROADNETS
2005
IEEE
15 years 8 months ago
Performance analysis and enhancement for backbone based wireless mobile ad hoc networks
—In this paper, we present an extended Mobile Backbone Network (MBN) topology synthesis algorithm (ETSA) for constructing and maintaining a dynamic backbone structure in mobile w...
Laura Huei-jiun Ju, Izhak Rubin
ISTA
2008
15 years 4 months ago
From Human Knowledge to Process Models
This contribution suggests a novel approach for a systematic generation of a process model in an informal environment. It is based on the claim that the knowledge about the process...
Jörg Desel
ERSA
2004
134views Hardware» more  ERSA 2004»
15 years 4 months ago
A High Performance Application Representation for Reconfigurable Systems
Modern reconfigurable computing systems feature powerful hybrid architectures with multiple microprocessor cores, large reconfigurable logic arrays and distributed memory hierarch...
Wenrui Gong, Gang Wang, Ryan Kastner
ICAD
2004
15 years 4 months ago
Decoupled Loudness and Range Control for a Source Located Within a Small Virtual Acoustic Environment
For headphone-based spatial auditory display systems, binaural synthesis of sound localization cues typically use source reproduction level as the primary control for source range...
William L. Martens