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HPCA
2001
IEEE
16 years 2 days ago
Reducing DRAM Latencies with an Integrated Memory Hierarchy Design
In this papel; we address the severe performance gap caused by high processor clock rates and slow DRAM accesses. We show that even with an aggressive, next-generation memory syst...
Wei-Fen Lin, Steven K. Reinhardt, Doug Burger
ICS
1999
Tsinghua U.
15 years 4 months ago
An experimental evaluation of tiling and shackling for memory hierarchy management
On modern computers, the performance of programs is often limited by memory latency rather than by processor cycle time. To reduce the impact of memory latency, the restructuring ...
Induprakas Kodukula, Keshav Pingali, Robert Cox, D...
ICS
2005
Tsinghua U.
15 years 5 months ago
The implications of working set analysis on supercomputing memory hierarchy design
Supercomputer architects strive to maximize the performance of scientific applications. Unfortunately, the large, unwieldy nature of most scientific applications has lead to the...
Richard C. Murphy, Arun Rodrigues, Peter M. Kogge,...
ECOOP
1987
Springer
15 years 3 months ago
Dynamic Grouping in an Object-Oriented Virtual Memory Hierarchy
Object oriented programming environments frequently suffer serious performance degradation because of a high level of paging activity when implemented using a conventional virtual...
Ifor Williams, Mario Wolczko, Trevor Hopkins
LCPC
1999
Springer
15 years 4 months ago
Inter-array Data Regrouping
Abstract. As the speed gap between CPU and memory widens, memory hierarchy has become the performance bottleneck for most applications because of both the high latency and low band...
Chen Ding, Ken Kennedy