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DAC
2008
ACM
15 years 10 months ago
An area-efficient high-throughput hybrid interconnection network for single-chip parallel processing
Single-chip parallel processing requires high bandwidth between processors and on-chip memory modules. A recently proposed Mesh-of-Trees (MoT) network provides high throughput and...
Aydin O. Balkan, Gang Qu, Uzi Vishkin
VLSID
2009
IEEE
96views VLSI» more  VLSID 2009»
15 years 10 months ago
Efficient Placement of Compressed Code for Parallel Decompression
Code compression is important in embedded systems design since it reduces the code size (memory requirement) and thereby improves overall area, power and performance. Existing res...
Xiaoke Qin, Prabhat Mishra
PPPJ
2009
ACM
15 years 4 months ago
Automatic parallelization for graphics processing units
Accelerated graphics cards, or Graphics Processing Units (GPUs), have become ubiquitous in recent years. On the right kinds of problems, GPUs greatly surpass CPUs in terms of raw ...
Alan Leung, Ondrej Lhoták, Ghulam Lashari
CEC
2008
IEEE
15 years 4 months ago
A parallel surrogate-assisted multi-objective evolutionary algorithm for computationally expensive optimization problems
Abstract— This paper presents a new efficient multiobjective evolutionary algorithm for solving computationallyintensive optimization problems. To support a high degree of parall...
Anna Syberfeldt, Henrik Grimm, Amos Ng, Robert Ivo...
ICC
2008
IEEE
115views Communications» more  ICC 2008»
15 years 4 months ago
Joint Power Scheduling and Estimator Design for Sensor Networks Across Parallel Channels
—This paper addresses the joint estimator and power optimization problem for a sensor network whose mission is to estimate an unknown parameter. We assume a two-hop network where...
Lauren M. Huie, Xiang He, Aylin Yener