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ISQED
2002
IEEE
83views Hardware» more  ISQED 2002»
15 years 8 months ago
A Hybrid BIST Architecture and Its Optimization for SoC Testing
This paper presents a hybrid BIST architecture and methods for optimizing it to test systems-on-chip in a cost effective way. The proposed self-test architecture can be implemente...
Gert Jervan, Zebo Peng, Raimund Ubar, Helena Kruus
129
Voted
IPPS
2006
IEEE
15 years 9 months ago
A pattern selection algorithm for multi-pattern scheduling
The multi-pattern scheduling algorithm is designed to schedule a graph onto a coarse-grained reconfigurable architecture, the result of which depends highly on the used patterns....
Yuanqing Guo, Cornelis Hoede, Gerard J. M. Smit
164
Voted
CICC
2011
106views more  CICC 2011»
14 years 3 months ago
A 45nm CMOS neuromorphic chip with a scalable architecture for learning in networks of spiking neurons
Efforts to achieve the long-standing dream of realizing scalable learning algorithms for networks of spiking neurons in silicon have been hampered by (a) the limited scalability of...
Jae-sun Seo, Bernard Brezzo, Yong Liu, Benjamin D....
145
Voted
IWPC
1998
IEEE
15 years 8 months ago
Pattern Visualization for Software Comprehension
Cognitive science emphasizes the strength of visual formalisms for human learning and problem solving. In software engineering, a clear, visual presentation of a system's arc...
Reinhard Schauer, Rudolf K. Keller
150
Voted
OOPSLA
2010
Springer
15 years 1 months ago
Towards a tool-based development methodology for sense/compute/control applications
This poster presents a design language and a tool suite covering the development life-cycle of a Sense/Compute/Control (SCC) application. This language makes it possible to define...
Damien Cassou, Julien Bruneau, Julien Mercadal, Qu...