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ISCAS
2005
IEEE
152views Hardware» more  ISCAS 2005»
15 years 3 months ago
Dictionary-based program compression on transport triggered architectures
— Program code size has become a critical design constraint of embedded systems. Large program codes require large memories, which increase the size and cost of the chip. Poor co...
Jari Heikkinen, Andrea G. M. Cilio, Jarmo Takala, ...
HIPC
2004
Springer
15 years 3 months ago
Performance Characteristics of a Cosmology Package on Leading HPC Architectures
Abstract. The Cosmic Microwave Background (CMB) is a snapshot of the Universe some 400,000 years after the Big Bang. The pattern of anisotropies in the CMB carries a wealth of info...
Jonathan Carter, Julian Borrill, Leonid Oliker
CASES
2007
ACM
15 years 2 months ago
Compiler generation from structural architecture descriptions
With increasing complexity of modern embedded systems, the availability of highly optimizing compilers becomes more and more important. At the same time, application specific inst...
Florian Brandner, Dietmar Ebner, Andreas Krall
EUROPAR
2010
Springer
14 years 11 months ago
Efficient Address Mapping of Shared Cache for On-Chip Many-Core Architecture
Abstract. Performance of the on-chip cache is critical for processor. The multithread program model usually employed by on-chip many-core architectures may have effects on cache ac...
Fenglong Song, Dongrui Fan, Zhiyong Liu, Junchao Z...
PDP
2010
IEEE
15 years 5 months ago
Skandium: Multi-core Programming with Algorithmic Skeletons
—This paper argues that algorithmic skeletons are a suitable programming model for multi-core architectures. -level abstractions offered by algorithmic skeletons provide a simple...
Mario Leyton, José M. Piquer