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ISLPED
2010
ACM
229views Hardware» more  ISLPED 2010»
15 years 3 months ago
An energy efficient cache design using spin torque transfer (STT) RAM
The on-chip memory is a dominant source of power and energy consumption in modern and future processors. This paper explores the use of a new emerging non-volatile memory technolo...
Mitchelle Rasquinha, Dhruv Choudhary, Subho Chatte...
VL
2010
IEEE
173views Visual Languages» more  VL 2010»
15 years 1 months ago
Modular Design by Contract Visually and Formally Using VCL
Visual representations are widely used to describe modern-day software systems, but, in most cases, they lack rigour. This paper addresses the problems of formality, rigour and co...
Nuno Amálio, Pierre Kelsen
ECRTS
1999
IEEE
15 years 7 months ago
QoS guarantee using probabilistic deadlines
This paper presents a probabilistic approach to guarantee the performance of a real-time system. While traditional real-time system analysis tends to guarantee that each task inst...
Luca Abeni, Giorgio C. Buttazzo
ICRE
1998
IEEE
15 years 7 months ago
Validating Requirements for Fault Tolerant Systems using Model Checking
Model checking is shown to be an effective tool in validating the behavior of a fault tolerant embedded spacecraft controller. The case study presented here at by judiciously abst...
Francis Schneider, Steve M. Easterbrook, John R. C...
IJES
2008
76views more  IJES 2008»
15 years 3 months ago
SoC multiprocessor debugging and synchronisation using generic dynamic-connect debugger frontends
: Current and future SoC designs will contain an increasing number of programmable units. To be able to tailor and debug these processors in their system context at the highest pos...
Andreas Wieferink, Tim Kogel, Olaf Zerres, Rainer ...