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FDL
2004
IEEE
15 years 1 months ago
A Formal Verification Approach for IP-based Designs
This paper proposes a formal verification methodology which is smoothly integrated with component-based system-level design, using a divide and conquer approach. The methodology a...
Daniel Karlsson, Petru Eles, Zebo Peng
GLVLSI
2007
IEEE
194views VLSI» more  GLVLSI 2007»
15 years 1 months ago
Probabilistic maximum error modeling for unreliable logic circuits
Reliability modeling and evaluation is expected to be one of the major issues in emerging nano-devices and beyond 22nm CMOS. Such devices would have inherent propensity for gate f...
Karthikeyan Lingasubramanian, Sanjukta Bhanja
GI
2007
Springer
15 years 1 months ago
The Use of Complex Stateflow-Charts with KIEL - An Automotive Case Study
Abstract: Modeling systems with Statecharts has become standard practice in the design of reactive embedded devices. However, the modeling of realistic applications with the paradi...
Steffen Prochnow, Reinhard von Hanxleden
TAICPART
2006
IEEE
144views Education» more  TAICPART 2006»
15 years 3 months ago
Testing the Implementation of Business Rules Using Intensional Database Tests
One of the key roles of any information system is to enforce the business rules and policies set by the owning organisation. As for any important functionality, it is necessary to...
David Willmor, Suzanne M. Embury
BMAS
2000
IEEE
15 years 2 months ago
High-Level Design Case of a Switched-Capacitor Low-Pass Filter Using Verilog-A
System design requires experienced designers that use heuristics and built up knowledge to propose a high order solution. Behavioral models can help to formalise, optimise and spe...
Erik Lauwers, Georges G. E. Gielen, Koen Lampaert,...