The L2 cache is commonly managed using LRU policy. For workloads that have a working set larger than L2 cache, LRU behaves poorly, resulting in a great number of less reused lines...
Chip multiprocessors (CMPs) substantially increase capacity pressure on the on-chip memory hierarchy while requiring fast access. Neither private nor shared caches can provide bot...
Zeshan Chishti, Michael D. Powell, T. N. Vijaykuma...
We reduce JavaScript to a core calculus structured as a small-step operational semantics. We present several peculiarities of the language and show that our calculus models them. W...
Technology advancements have enabled the integration of large on-die embedded DRAM (eDRAM) caches. eDRAM is significantly denser than traditional SRAMs, but must be periodically r...
Chris Wilkerson, Alaa R. Alameldeen, Zeshan Chisht...
Material Flow Abstraction of Manufacturing Systems. ‣Umberto Costa, Ivan de Medeiros Jr and Marcel Oliveira. Specification and Verification of a MPI Implementation for a MP-SoC...