1895 search results - page 76 / 379 » Using ATL for Checking Models |
113
Voted
ISQED
2003
IEEE
15 years 8 months ago
2003
IEEE
This paper describes the use of integer equations for high level modeling digital circuits for application of formal verification properties at this level. Most formal verificatio...
126
Voted
MTV
2006
IEEE
15 years 8 months ago
2006
IEEE
In this paper we will present an optimized structural 01X-SAT-solver for bounded model checking of blackbox designs that exploits semantical knowledge regarding the node selection...
132
Voted
SIGPLAN
2002
15 years 2 months ago
2002
Future Interval Logic (FIL) and its intuitive graphical representation, Graphical Interval Logic (GIL), can be used as the formal description language of model checking tools to v...
115
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MEMOCODE
2007
IEEE
15 years 9 months ago
2007
IEEE
The always increasing complexity of digital system is overcome in design flows based on Transaction Level Modeling (TLM) by designing and verifying the system at difbstraction le...
101
Voted
VTC
2007
IEEE
15 years 9 months ago
2007
IEEE
— Wireless transmission based on cooperation promises to bring performance improvements in multi–node networks. Several cooperative schemes have appeared in the literature, and...