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» Using Cell-DEVS for Modeling Complex Cell Spaces
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ICCAD
1995
IEEE
134views Hardware» more  ICCAD 1995»
15 years 3 months ago
A delay model for logic synthesis of continuously-sized networks
ng certain electrical noise and power constraints.Abstract: We present a new delay model for use in logic synthesis. A traditional model treats the area of a library cell as consta...
Joel Grodstein, Eric Lehman, Heather Harkness, Bil...
HPCC
2007
Springer
15 years 5 months ago
Towards a Complexity Model for Design and Analysis of PGAS-Based Algorithms
Many new Partitioned Global Address Space (PGAS) programming languages have recently emerged and are becoming ubiquitously available on nearly all modern parallel architectures. PG...
Mohamed Bakhouya, Jaafar Gaber, Tarek A. El-Ghazaw...
IISWC
2008
IEEE
15 years 6 months ago
Accelerating multi-core processor design space evaluation using automatic multi-threaded workload synthesis
The design and evaluation of microprocessor architectures is a difficult and time-consuming task. Although small, handcoded microbenchmarks can be used to accelerate performance e...
Clay Hughes, Tao Li
125
Voted
TRS
2008
14 years 11 months ago
The Neurophysiological Bases of Cognitive Computation Using Rough Set Theory
A popular view is that the brain works in a similar way to a digital computer or a Universal Turing Machine by processing symbols. Psychophysical experiments and our amazing capabi...
Andrzej W. Przybyszewski
DATE
2009
IEEE
112views Hardware» more  DATE 2009»
15 years 6 months ago
Test exploration and validation using transaction level models
—The complexity of the test infrastructure and test strategies in systems-on-chip approaches the complexity of the functional design space. This paper presents test design space ...
Michael A. Kochte, Christian G. Zoellin, Michael E...