Load imbalance that deteriorates the system performance is a severe problem existing in 3GPP LTE networks. To deal with this problem, we propose in this paper a load balancing fra...
Hao Wang, Lianghui Ding, Ping Wu, Zhiwen Pan, Nan ...
Future CMPs will combine many simple cores with deep cache hierarchies. With more cores, cache resources per core are fewer, and must be shared carefully to avoid poor utilization...
Junli Gu, Steven S. Lumetta, Rakesh Kumar, Yihe Su...
Abstract—As Chip-Multiprocessor systems (CMP) have become the predominant topology for leading microprocessors, critical components of the system are now integrated on a single c...
Dimitris Kaseridis, Jeffrey Stuecheli, Lizy K. Joh...
In an intelligent memory architecture, the main memory of a computer is enhanced with many simple processors. The result is a highly-parallel, heterogeneous machine that is able t...
Basilio B. Fraguela, Jose Renau, Paul Feautrier, D...
The performance requirements for contemporary microprocessors are increasing as rapidly as their number of applications grows. By accelerating the clock, performance can be gained...