Sciweavers

126 search results - page 13 / 26
» Using Formal Tools to Study Complex Circuits Behaviour
Sort
View
69
Voted
EPEW
2005
Springer
15 years 5 months ago
Automatic Translation of WS-CDL Choreographies to Timed Automata
In this paper we show how we can translate Web Services described by WS-CDL into a timed automata orchestration, and more specifically we are interested in Web services with time ...
Gregorio Díaz, Juan José Pardo, Mar&...
104
Voted
APN
2006
Springer
15 years 3 months ago
On the Integration of UML and Petri Nets in Software Development
Abstract. Software performance engineering deals with the consideration of quantitative analysis of the behaviour of software systems from the early development phases in the life ...
Javier Campos, José Merseguer
AIED
2005
Springer
15 years 5 months ago
Towards support in building qualitative knowledge models
Qualitative Reasoning (QR) formalisms provide ontological primitives for capturing conceptual knowledge. Recently QR-based diagrammatic tools are being developed to support learne...
Vania Bessa Machado, Roland Groen, Bert Bredeweg
ECMDAFA
2009
Springer
170views Hardware» more  ECMDAFA 2009»
15 years 6 months ago
A Model Driven Approach to the Analysis of Timeliness Properties
The need for a design language that is rigorous but accessible and intuitive is often at odds with the formal and mathematical nature of languages used for analysis. UML and Petri ...
Mohamed Ariff Ameedeen, Behzad Bordbar, Rachid Ana...
147
Voted
ISPD
2012
ACM
288views Hardware» more  ISPD 2012»
13 years 7 months ago
Construction of realistic gate sizing benchmarks with known optimal solutions
Gate sizing in VLSI design is a widely-used method for power or area recovery subject to timing constraints. Several previous works have proposed gate sizing heuristics for power ...
Andrew B. Kahng, Seokhyeong Kang