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IEEEPACT
2008
IEEE
15 years 4 months ago
Scalable and reliable communication for hardware transactional memory
In a hardware transactional memory system with lazy versioning and lazy conflict detection, the process of transaction commit can emerge as a bottleneck. This is especially true ...
Seth H. Pugsley, Manu Awasthi, Niti Madan, Naveen ...
ISCA
1994
IEEE
129views Hardware» more  ISCA 1994»
15 years 1 months ago
Software Versus Hardware Shared-Memory Implementation: A Case Study
We comparethe performance of software-supported shared memory on a general-purpose network to hardware-supported shared memory on a dedicated interconnect. Up to eight processors,...
Alan L. Cox, Sandhya Dwarkadas, Peter J. Keleher, ...
MICRO
2008
IEEE
111views Hardware» more  MICRO 2008»
15 years 4 months ago
Reducing the harmful effects of last-level cache polluters with an OS-level, software-only pollute buffer
It is well recognized that LRU cache-line replacement can be ineffective for applications with large working sets or non-localized memory access patterns. Specifically, in lastle...
Livio Soares, David K. Tam, Michael Stumm
ICCAD
2004
IEEE
114views Hardware» more  ICCAD 2004»
15 years 6 months ago
High-level synthesis using computation-unit integrated memories
Abstract— High-level synthesis (HLS) of memory-intensive applications has featured several innovations in terms of enhancements made to the basic memory organization and data lay...
Chao Huang, Srivaths Ravi, Anand Raghunathan, Nira...

Presentation
1575views
16 years 8 months ago
Beyond Generating Transit Performance Measures: Visualizations and Statistical Analysis using Historical Data
In recent years, the use of performance measures for transit planning and operations has gained a great deal of attention, particularly as transit agencies are required to provide ...
M. Berkow, A. El-Geneidy, R.L. Bertini, D. Crout