459 search results - page 90 / 92 » Using Kernel Couplings to Predict Parallel Application Perfo... |
95
Voted
CODES
2005
IEEE
15 years 3 months ago
2005
IEEE
Arbitrary memory dependencies and variable latency memory systems are major obstacles to the synthesis of large-scale ASIC systems in high-level synthesis. This paper presents SOM...
107
Voted
ISORC
2007
IEEE
15 years 3 months ago
2007
IEEE
Many emerging applications operate on continuous unbounded data streams and need real-time data services. Providing deadline guarantees for queries over dynamic data streams is a ...
ISCA
2008
IEEE
15 years 3 months ago
2008
IEEE
Multicore processors have emerged as a powerful platform on which to efficiently exploit thread-level parallelism (TLP). However, due to Amdahl’s Law, such designs will be incr...
ICS
2003
Tsinghua U.
15 years 2 months ago
2003
Tsinghua U.
We describe the architecture for a single-chip aegis processor which can be used to build computing systems secure against both physical and software attacks. Our architecture ass...
TCAD
2010
14 years 4 months ago
2010
Abstract--This paper presents a GALS-compatible circuitswitched on-chip network that is well suited for use in many-core platforms targeting streaming DSP and embedded applications...