Sciweavers

785 search results - page 86 / 157
» Using Multiple Levels of Abstractions in Embedded Software D...
Sort
View
CODES
2008
IEEE
15 years 4 months ago
Static analysis for fast and accurate design space exploration of caches
Application-specific system-on-chip platforms create the opportunity to customize the cache configuration for optimal performance with minimal chip estate. Simulation, in partic...
Yun Liang, Tulika Mitra
CGO
2008
IEEE
15 years 4 months ago
Compiling for vector-thread architectures
Vector-thread (VT) architectures exploit multiple forms of parallelism simultaneously. This paper describes a compiler for the Scale VT architecture, which takes advantage of the ...
Mark Hampton, Krste Asanovic
FPL
2009
Springer
104views Hardware» more  FPL 2009»
15 years 2 months ago
A multi-layered XML schema and design tool for reusing and integrating FPGA IP
Reconfigurable computing systems remain difficult to use and program. One way to increase design productivity for these systems is through reuse of previously developed and veri...
Adam Arnesen, Nathan Rollins, Michael J. Wirthlin
SENSYS
2004
ACM
15 years 3 months ago
Hardware design experiences in ZebraNet
The enormous potential for wireless sensor networks to make a positive impact on our society has spawned a great deal of research on the topic, and this research is now producing ...
Pei Zhang, Christopher M. Sadler, Stephen A. Lyon,...
FPL
2004
Springer
125views Hardware» more  FPL 2004»
15 years 3 months ago
SoftSONIC: A Customisable Modular Platform for Video Applications
This paper presents the Customisable Modular Platform (CMP) approach. The aim is to accelerate FPGA application developraising the level of abstraction and facilitating design reus...
Tero Rissa, Peter Y. K. Cheung, Wayne Luk