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112
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ISVLSI
2006
IEEE
126views VLSI» more  ISVLSI 2006»
15 years 8 months ago
QUKU: A Two-Level Reconfigurable Architecture
FPGAs have been used for prototyping of ASICs, for low-volume ASIC replacement and for systems requiring in-field hardware upgrades. However, the potential to use dynamic reconfig...
Sunil Shukla, Neil W. Bergmann, Jürgen Becker
187
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TITB
2002
172views more  TITB 2002»
15 years 1 months ago
Shape recovery algorithms using level sets in 2-D/3-D medical imagery: a state-of-the-art review
The class of geometric deformable models, also known as level sets, has brought tremendous impact to medical imagery due to its capability of topology preservation and fast shape r...
Jasjit S. Suri, Kecheng Liu, Sameer Singh, Swamy L...
HASE
1999
IEEE
15 years 6 months ago
Building Dependable Distributed Applications Using AQUA
Building dependable distributed systems using ad hoc methods is a challenging task. Without proper support, an application programmer must face the daunting requirement of having ...
Jennifer Ren, Michel Cukier, Paul Rubel, William H...
VLSID
2009
IEEE
177views VLSI» more  VLSID 2009»
16 years 2 months ago
Accelerating System-Level Design Tasks Using Commodity Graphics Hardware: A Case Study
Many system-level design tasks (e.g. timing analysis, hardware/software partitioning and design space exploration) involve computational kernels that are intractable (usually NP-ha...
Unmesh D. Bordoloi, Samarjit Chakraborty
DSD
2010
IEEE
162views Hardware» more  DSD 2010»
15 years 13 days ago
A Parallel for Loop Memory Template for a High Level Synthesis Compiler
—We propose a parametrized memory template for applications with parallel for loops. The template’s parameters reflect important trade-offs made during system design. The temp...
Craig Moore, Wim Meeus, Harald Devos, Dirk Strooba...