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» Using Prediction to Accelerate Coherence Protocols
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ICCD
2008
IEEE
159views Hardware» more  ICCD 2008»
14 years 3 months ago
Optimizing data sharing and address translation for the Cell BE Heterogeneous Chip Multiprocessor
— Heterogeneous Chip Multiprocessors (HMPs), such as the Cell Broadband Engine, offer a new design optimization opportunity by allowing designers to provide accelerators for appl...
Michael Gschwind
DAIS
2006
13 years 7 months ago
Using Speculative Push for Unnecessary Checkpoint Creation Avoidance
Abstract. This paper discusses a way of incorporating speculation techniques into Distributed Shared Memory (DSM) systems with checkpointing mechanism without creating unnecessary ...
Arkadiusz Danilecki, Michal Szychowiak
MICRO
2009
IEEE
133views Hardware» more  MICRO 2009»
14 years 1 months ago
A tagless coherence directory
A key challenge in architecting a CMP with many cores is maintaining cache coherence in an efficient manner. Directory-based protocols avoid the bandwidth overhead of snoop-based ...
Jason Zebchuk, Vijayalakshmi Srinivasan, Moinuddin...
CC
2008
Springer
144views System Software» more  CC 2008»
13 years 8 months ago
Control Flow Emulation on Tiled SIMD Architectures
Heterogeneous multi-core and streaming architectures such as the GPU, Cell, ClearSpeed, and Imagine processors have better power/ performance ratios and memory bandwidth than tradi...
Ghulam Lashari, Ondrej Lhoták, Michael McCo...
VLDB
2012
ACM
360views Database» more  VLDB 2012»
12 years 2 months ago
An adaptive updating protocol for reducing moving object database workload
In the last decade, spatio-temporal database research focuses on the design of effective and efficient indexing structures in support of location-based queries such as predictive...
Su Chen, Beng Chin Ooi, Zhenjie Zhang