Sciweavers

50 search results - page 7 / 10
» Using SCTP to hide latency in MPI programs
Sort
View
HPDC
2012
IEEE
13 years 1 days ago
vSlicer: latency-aware virtual machine scheduling via differentiated-frequency CPU slicing
Recent advances in virtualization technologies have made it feasible to host multiple virtual machines (VMs) in the same physical host and even the same CPU core, with fair share ...
Cong Xu, Sahan Gamage, Pawan N. Rao, Ardalan Kanga...
ISCA
2003
IEEE
110views Hardware» more  ISCA 2003»
15 years 2 months ago
Guided Region Prefetching: A Cooperative Hardware/Software Approach
Despite large caches, main-memory access latencies still cause significant performance losses in many applications. Numerous hardware and software prefetching schemes tolerate th...
Zhenlin Wang, Doug Burger, Steven K. Reinhardt, Ka...
PDCN
2004
14 years 11 months ago
Improving http-server performance by adapted multithreading
It is wellknown that http servers can be programmed easier by using multithreading, i.e. each connection is dealt with by a separate thread. It is also known, e.g. from massively ...
Jörg Keller, Olaf Monien
CF
2007
ACM
15 years 1 months ago
Accelerating memory decryption and authentication with frequent value prediction
This paper presents a novel architectural technique to hide fetch latency overhead of hardware encrypted and authenticated memory. A number of recent secure processor designs have...
Weidong Shi, Hsien-Hsin S. Lee
HPCA
1999
IEEE
15 years 2 months ago
Impulse: Building a Smarter Memory Controller
Impulse is a new memory system architecture that adds two important features to a traditional memory controller. First, Impulse supports application-specific optimizations through...
John B. Carter, Wilson C. Hsieh, Leigh Stoller, Ma...