50 search results - page 8 / 10 » Using SCTP to hide latency in MPI programs |
PARA
2004
Springer
15 years 3 months ago
2004
Springer
Cache optimizations typically include code transformations to increase the locality of memory accesses. An orthogonal approach is to enable for latency hiding by introducing prefet...
ISCA
2000
IEEE
15 years 2 months ago
2000
IEEE
For many applications, branch mispredictions and cache misses limit a processor’s performance to a level well below its peak instruction throughput. A small fraction of static i...
ICPP
2003
IEEE
15 years 2 months ago
2003
IEEE
Hardware prefetching is a simple and effective technique for hiding cache miss latency and thus improving the overall performance. However, it comes with addition of prefetch buff...
DSN
2002
IEEE
15 years 2 months ago
2002
IEEE
Concentration of design effort for current single-chip Commercial-Off-The-Shelf (COTS) microprocessors has been directed towards performance. Reliability has not been the primary ...
PC
2010
14 years 8 months ago
2010
Compute unified device architecture (CUDA) is a software development platform that allows us to run C-like programs on the nVIDIA graphics processing unit (GPU). This paper prese...