453 search results - page 12 / 91 » Using Symbolic Simulation for Bounded Property Checking |
91
Voted
GLVLSI
2006
IEEE
15 years 5 months ago
2006
IEEE
Functional verification is one of the major bottlenecks in microprocessor design. Simulation-based techniques are the most widely used form of processor verification. Efficient ...
116
Voted
RTSS
2008
IEEE
15 years 6 months ago
2008
IEEE
In this paper, we address the problem of symbolically computing the region in the parameter’s space that guarantees a feasible schedule, given a set of real-time tasks character...
106
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ICFEM
2009
Springer
14 years 9 months ago
2009
Springer
In this paper we continue the study of a strict extension of the Computation Tree Logic, called graded-CTL, recently introduced by the same authors. This new logic augments the sta...
FMCAD
2004
Springer
15 years 5 months ago
2004
Springer
We consider the problem of checking whether an incomplete design can still be extended to a complete design satisfying a given CTL formula and whether the property is satisfied fo...
101
Voted
CAV
1998
Springer
15 years 3 months ago
1998
Springer
bstract description of state machines (ASMs), in which data and data operations are d using abstract sort and uninterpreted function symbols. ASMs are suitable for describing Regis...