Sciweavers

453 search results - page 48 / 91
» Using Symbolic Simulation for Bounded Property Checking
Sort
View
DC
2010
14 years 12 months ago
Model checking transactional memories
Model checking software transactional memories (STMs) is difficult because of the unbounded number, length, and delay of concurrent transactions and the unbounded size of the memo...
Rachid Guerraoui, Thomas A. Henzinger, Vasu Singh
DAC
2008
ACM
16 years 23 days ago
Construction of concrete verification models from C++
C++ based verification methodologies are now emerging as the preferred method for SOC design. However most of the verification involving the C++ models are simulation based. The c...
Malay Haldar, Gagandeep Singh, Saurabh Prabhakar, ...
CCS
2011
ACM
13 years 11 months ago
Trace equivalence decision: negative tests and non-determinism
We consider security properties of cryptographic protocols that can be modeled using the notion of trace equivalence. The notion of equivalence is crucial when specifying privacy-...
Vincent Cheval, Hubert Comon-Lundh, Stéphan...
JSC
2010
100views more  JSC 2010»
14 years 6 months ago
An invariant-based approach to the verification of asynchronous parameterized networks
A uniform verification problem for parameterized systems is to determine whether a temporal property is satisfied for every instance of the system which is composed of an arbitrar...
Igor V. Konnov, Vladimir A. Zakharov
FORMATS
2006
Springer
15 years 3 months ago
Temporal Logic Verification Using Simulation
In this paper, we consider a novel approach to the temporal logic verification problem of continuous dynamical systems. Our methodology has the distinctive feature that enables the...
Georgios E. Fainekos, Antoine Girard, George J. Pa...