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DAC
2002
ACM
16 years 5 months ago
A framework for evaluating design tradeoffs in packet processing architectures
We present an analytical method to evaluate embedded network packet processor architectures, and to explore their design space. Our approach is in contrast to those based on simul...
Lothar Thiele, Matthias Gries, Samarjit Chakrabort...
SAMOS
2007
Springer
15 years 10 months ago
Mapping and Performance Evaluation for Heterogeneous MP-SoCs Via Packing
The computational demand of signal processing algorithms is rising continuously. Heterogeneous embedded multiprocessor systems-on-chips are one solution to tackle this demand. But ...
Bastian Ristau, Gerhard Fettweis
WWW
2003
ACM
16 years 4 months ago
SHOCK: communicating with computational messages and automatic private profiles
A computationally enhanced message contains some embedded programmatic components that are interpreted and executed automatically upon receipt. Unlike ordinary text email or insta...
Rajan M. Lukose, Eytan Adar, Joshua R. Tyler, Caes...
IWSOC
2003
IEEE
132views Hardware» more  IWSOC 2003»
15 years 9 months ago
A Catalog of Hardware Acceleration Techniques for Real-Time Reconfigurable System on Chip
The new technology of reconfigurable System-on-Chip is shown to be a good match to the requirements of realtime embedded systems. In particular, the judicious use of specialised d...
Neil W. Bergmann, Peter Waldeck, John A. Williams
RTAS
1998
IEEE
15 years 8 months ago
FARA - A Framework for Adaptive Resource Allocation in Complex Real-Time Systems
This paper introduces FARA, a framework that provides abstractions and mechanisms for building integrated adaptation and resource allocation services in complex real-time systems....
Daniela Rosu, Karsten Schwan, Sudhakar Yalamanchil...