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ICCAD
2008
IEEE
147views Hardware» more  ICCAD 2008»
16 years 1 months ago
Overlay aware interconnect and timing variation modeling for double patterning technology
— As Double Patterning Technology (DPT) becomes the only solution for 32-nm lithography process, we need to investigate how DPT affects the performance of a chip. In this paper, ...
Jae-Seok Yang, David Z. Pan
BSN
2009
IEEE
137views Sensor Networks» more  BSN 2009»
15 years 11 months ago
Technologies for an Autonomous Wireless Home Healthcare System
We present a design study highlighting our recent technological developments that will enable the implementation of autonomous wireless sensor networks for home healthcare monitori...
Christine Ho, Michael Mark, Michael Koplow, Lindsa...
CISIS
2009
IEEE
15 years 11 months ago
Designing Regular Network-on-Chip Topologies under Technology, Architecture and Software Constraints
—Regular multi-core processors are appearing in the embedded system market as high performance software programmable solutions. The use of regular interconnect fabrics for them a...
Francisco Gilabert Villamón, Daniele Ludovi...
IEEESCC
2007
IEEE
15 years 10 months ago
Brave New Web: Emerging Design Principles and Technologies as Enablers of a Global SOA
Web Services have experienced great interest during the last years as they were expected to play a key role as enablers of seamless application-to-application integration both wit...
Christoph Schroth, Oliver Christ
SAMOS
2007
Springer
15 years 10 months ago
A Simulation-Based Methodology for Evaluating the DPA-Resistance of Cryptographic Functional Units with Application to CMOS and
Abstract— This paper explores the resistance of MOS Current Mode Logic (MCML) against Differential Power Analysis (DPA) attacks. Circuits implemented in MCML, in fact, have uniqu...
Francesco Regazzoni, Stéphane Badel, Thomas...