259 search results - page 13 / 52 » Using Transformations and Verification in Circuit Design |
JIRS
2007
15 years 8 days ago
2007
A detailed step-by-step approach is presented to optimize, standardize, and automate the process of unmanned vehicle controller design, evaluation, validation and verification, fol...
101
Voted
ICCAD
1998
IEEE
15 years 4 months ago
1998
IEEE
Retiming and resynthesis transformations can be used for optimizing the area, power, and delay of sequential circuits. Even though this technique has been known for more than a de...
148
Voted
DAC
2006
ACM
16 years 1 months ago
2006
ACM
- Classical two-variable symmetries play an important role in many EDA applications, ranging from logic synthesis to formal verification. This paper proposes a complete circuit-bas...
89
Voted
DAC
2005
ACM
16 years 1 months ago
2005
ACM
This paper presents an efficient hierarchical 3D capacitance extraction algorithm -- ICCAP. Most previous capacitance extraction algorithms introduce intermediate variables to fac...
94
Voted
DAC
2009
ACM
16 years 1 months ago
2009
ACM
Boolean satisfiability (SAT) solvers are used heavily in hardware and software verification tools for checking satisfiability of Boolean formulas. Most state-of-the-art SAT solver...