259 search results - page 17 / 52 » Using Transformations and Verification in Circuit Design |
105
Voted
DAC
1999
ACM
16 years 1 months ago
1999
ACM
This paper describes a novel methodology for high performance asynchronous design based on timed circuits and on CAD support for their synthesis using Relative Timing. This method...
112
Voted
VLSID
2002
IEEE
16 years 23 days ago
2002
IEEE
Satisfiability of complex word-level formulas often arises as a problem in formal verification of hardware designs described at the register transfer level (RTL). Even though most...
130
Voted
DATE
2009
IEEE
15 years 4 months ago
2009
IEEE
In the digital VLSI cycle, logic transformations are often required to modify the design to meet different synthesis and optimization goals. Logic transformations on sequential ci...
ICCAD
2005
IEEE
15 years 9 months ago
2005
IEEE
— This paper addresses the problem of equivalence verification of RTL descriptions. The focus is on datapathoriented designs that implement polynomial computations over fixed-s...
88
Voted
FMCAD
2000
Springer
15 years 4 months ago
2000
Springer
BLIF is a hardware description language designed for the hierarchical description of sequential circuits. We give a denotational semantics for BLIF-MV, a popular dialect of BLIF, t...