259 search results - page 18 / 52 » Using Transformations and Verification in Circuit Design |
SIMUTOOLS
2008
15 years 1 months ago
2008
Model checking is a suitable formal technique to analyze parallel programs' execution in an industrial context because automated tools can be designed and operated with very ...
124
Voted
CODES
2008
IEEE
15 years 2 months ago
2008
IEEE
SystemC is widely used for modeling and simulation in hardware/software co-design. Due to the lack of a complete formal semantics, it is not possible to verify SystemC designs. In...
106
click to vote
CSI
2008
15 years 14 days ago
2008
An identity-based (ID-based) universal designated verifier signature (ID-UDVS) scheme allows a signature holder to designate a specific verifier of the signature by using a simpli...
94
Voted
ICCD
2004
IEEE
15 years 9 months ago
2004
IEEE
This paper proposes a new formalism for layout-driven optimization of datapaths. It is based on preserving an arithmetic bit level representation of the arithmetic circuit portion...
109
Voted
TCAD
2002
15 years 1 days ago
2002
Many tasks in CAD, such as equivalence checking, property checking, logic synthesis, and false paths analysis require efficient Boolean reasoning for problems derived from circuits...