259 search results - page 19 / 52 » Using Transformations and Verification in Circuit Design |
111
Voted
DAC
2004
ACM
16 years 1 months ago
2004
ACM
Current Static Timing Analysis (STA) techniques allow one to verify the timing of a circuit at different process corners which only consider cases where all the supplies are low o...
DFT
1998
IEEE
15 years 4 months ago
1998
IEEE
This paper presents a system to evaluate the testability of an on-line testable circuit. The system operates at the RT-level, before the logic synthesis step, and allows for an ex...
111
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DAC
2003
ACM
15 years 5 months ago
2003
ACM
A new methodology is presented to solve a strongly nonlinear circuit, characterized by Piece-Wise Linear (PWL) functions, symbolically and explicitly in terms of its circuit param...
108
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FPL
2009
Springer
15 years 5 months ago
2009
Springer
In this paper we present a verification platform designed for HyperTransport 3.x (HT3) applications. HyperTransport 3.x is a very low latency and high bandwidth chip-tochip interc...
105
Voted
ICCAD
1996
IEEE
15 years 4 months ago
1996
IEEE
State justification is a time-consuming operation in test generation for sequential circuits. In this paper, we present a technique to rapidly identify state elements (flip-flops)...