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» Using Transformations and Verification in Circuit Design
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DATE
2000
IEEE
132views Hardware» more  DATE 2000»
15 years 4 months ago
Automatic Test Bench Generation for Validation of RT-Level Descriptions: An Industrial Experience
In current microprocessors and systems, an increasingly high silicon portion is derived through automatic synthesis, with designers working exclusively at the RT-level, and design...
Fulvio Corno, Matteo Sonza Reorda, Giovanni Squill...
88
Voted
ETS
2010
IEEE
140views Hardware» more  ETS 2010»
15 years 1 months ago
Increasing reliability of programmable mixed-signal systems by applying design diversity redundancy
This paper explores the concept of design diversity redundancy applied to mixed-signal (MS) circuit blocks, as a proposal to increase system reliability. Three different implement...
Gabriel de M. Borges, Luiz F. Gonçalves, Ti...
VLSID
2009
IEEE
155views VLSI» more  VLSID 2009»
16 years 1 months ago
Unified Challenges in Nano-CMOS High-Level Synthesis
: The challenges in nano-CMOS circuit design include the following: variability, leakage, power, thermals, reliability, and yield. This talk will focus on interdependent considerat...
Saraju P. Mohanty
135
Voted
DAC
2004
ACM
15 years 4 months ago
Communication-efficient hardware acceleration for fast functional simulation
This paper presents new technology that accelerates system verification. Traditional methods for verifying functional designs are based on logic simulation, which becomes more tim...
Young-Il Kim, Woo-Seung Yang, Young-Su Kwon, Chong...
102
Voted
DAC
1998
ACM
15 years 4 months ago
OCCOM: Efficient Computation of Observability-Based Code Coverage Metrics for Functional Verification
—Functional simulation is still the primary workhorse for verifying the functional correctness of hardware designs. Functional verification is necessarily incomplete because it i...
Farzan Fallah, Srinivas Devadas, Kurt Keutzer