259 search results - page 28 / 52 » Using Transformations and Verification in Circuit Design |
ASPDAC
2010
ACM
14 years 10 months ago
2010
ACM
This paper describes gate work function and oxide thickness tuning to realize novel circuits using dual-Vth independent-gate FinFETs. Dual-Vth FinFETs with independent gates enabl...
133
Voted
CL
2010
Springer
15 years 16 days ago
2010
Springer
In this paper we present the syntax, semantics, and compilation of a new system-level programming language called SystemJ. SystemJ is a multiclock language supporting the Globally...
100
click to vote
CORR
2010
Springer
14 years 10 months ago
2010
Springer
This paper discusses highly general mechanisms for specifying the refinement of a real-time system as a collection of lower level parallel components that preserve the timing and ...
117
Voted
AOSD
2009
ACM
15 years 7 months ago
2009
ACM
e is an aspect-oriented hardware verification language that is widely used to verify the design of electronic circuits through the development and execution of testbenches. In rec...
121
click to vote
VLSID
2002
IEEE
15 years 5 months ago
2002
IEEE
We propose a timing-oriented logic optimization technique called Generalized De Morgan (GDM) transform, that integrates gate resizing, net buffering and De Morgan transformation. ...