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» Using Transformations and Verification in Circuit Design
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95
Voted
DAC
1998
ACM
16 years 1 months ago
Combining Theorem Proving and Trajectory Evaluation in an Industrial Environment
We describe the verification of the IM: a large, complex (12,000 gates and 1100 latches) circuit that detects and marks the boundaries between Intel architecture (IA-32) instructi...
Mark Aagaard, Robert B. Jones, Carl-Johan H. Seger
100
Voted
ICCAD
1999
IEEE
80views Hardware» more  ICCAD 1999»
15 years 4 months ago
What is the cost of delay insensitivity?
Deep submicron technology calls for new design techniques, in which wire and gate delays are accounted to have equal or nearly equal effect on circuit behaviour. Asynchronous spee...
Hiroshi Saito, Alex Kondratyev, Jordi Cortadella, ...
108
Voted
BIRTHDAY
2007
Springer
15 years 4 months ago
Applying a Theorem Prover to the Verification of Optimistic Replication Algorithms
Abstract. The Operational Transformation (OT) approach is a technique for supporting optimistic replication in collaborative and mobile systems. It allows the users to concurrently...
Abdessamad Imine, Michaël Rusinowitch
EMSOFT
2004
Springer
15 years 4 months ago
A methodology for generating verified combinatorial circuits
High-level programming languages offer significant expressivity but provide little or no guarantees about resource use. Resourcebounded languages -- such as hardware-description l...
Oleg Kiselyov, Kedar N. Swadi, Walid Taha
118
Voted
MEMOCODE
2010
IEEE
14 years 10 months ago
Proving transaction and system-level properties of untimed SystemC TLM designs
Electronic System Level (ESL) design manages the complexity of todays systems by using abstract models. In this context Transaction Level Modeling (TLM) is state-of-theart for desc...
Daniel Große, Hoang M. Le, Rolf Drechsler