259 search results - page 34 / 52 » Using Transformations and Verification in Circuit Design |
118
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WOSP
2005
ACM
15 years 6 months ago
2005
ACM
The change of focus from code to models promoted by OMG's Model Driven Development raises the need for verification of nonfunctional characteristics of UML models, such as pe...
96
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DAC
2007
ACM
16 years 1 months ago
2007
ACM
The bus tracing is used to catch related signals for further investigation and analysis. However, the trace size of cycleaccurate tracing is large and the trace cycle is shallow u...
96
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DAC
2006
ACM
16 years 1 months ago
2006
ACM
Formal languages are increasingly used to describe the functional requirements (specifications) of circuits. These requirements are used as a means to communicate design intent an...
98
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DAC
2006
ACM
16 years 1 months ago
2006
ACM
SAT sweeping is a method for simplifying an AND/INVERTER graph (AIG) by systematically merging graph vertices from the inputs towards the outputs using a combination of structural...
97
Voted
DAC
2005
ACM
16 years 1 months ago
2005
ACM
el Predicate Abstraction and Refinement for Verifying RTL Verilog Himanshu Jain CMU SCS, Pittsburgh, PA 15213 Daniel Kroening ETH Z?urich, Switzerland Natasha Sharygina CMU SCS an...