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» Using Transformations and Verification in Circuit Design
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83
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ASPDAC
2004
ACM
87views Hardware» more  ASPDAC 2004»
15 years 6 months ago
ShatterPB: symmetry-breaking for pseudo-Boolean formulas
Many important tasks in circuit design and verification can be performed in practice via reductions to Boolean Satisfiability (SAT), making SAT a fundamental EDA problem. However ...
Fadi A. Aloul, Arathi Ramani, Igor L. Markov, Kare...
GLVLSI
2003
IEEE
180views VLSI» more  GLVLSI 2003»
15 years 5 months ago
3D direct vertical interconnect microprocessors test vehicle
The current trends in high performance integrated circuits are towards faster and more powerful circuits in the giga-hertz range and even further. As the more complex Integrated C...
John Mayega, Okan Erdogan, Paul M. Belemjian, Kuan...
110
Voted
ICCD
2003
IEEE
123views Hardware» more  ICCD 2003»
15 years 9 months ago
Simplifying SoC design with the Customizable Control Processor Platform
With the circuit density available in today’s ASIC design systems, increased integration is possible creating more complexity in the design of a System on a Chip (SoC). IBM’s ...
C. Ross Ogilvie, Richard Ray, Robert Devins, Mark ...
DAC
2004
ACM
16 years 1 months ago
STAC: statistical timing analysis with correlation
Current technology trends have led to the growing impact of both inter-die and intra-die process variations on circuit performance. While it is imperative to model parameter varia...
Jiayong Le, Xin Li, Lawrence T. Pileggi
DAC
1991
ACM
15 years 4 months ago
REX - A VLSI Parasitic Extraction Tool for Electromigration and Signal Analysis
REX is a program that extracts parasitic resistance and capacitance values for nodes in VLSI layouts. REX also performs network serial and parallel simplifications. Two types of n...
Jerry P. Hwang