Sciweavers

259 search results - page 43 / 52
» Using Transformations and Verification in Circuit Design
Sort
View
98
Voted
DAC
2005
ACM
16 years 1 months ago
Advanced Timing Analysis Based on Post-OPC Extraction of Critical Dimensions
While performance specifications are verified before sign-off for a modern nanometer scale design, extensive application of optical proximity correction substantially alters the l...
Puneet Gupta, Andrew B. Kahng, Youngmin Kim, Denni...
DATE
2006
IEEE
108views Hardware» more  DATE 2006»
15 years 6 months ago
Software-friendly HW/SW co-simulation: an industrial case study
This paper proposes a novel HW/SW co-simulation approach that minimizes the impact on software designers. We propose a SystemC-based system that enables the software team to test ...
Juanjo Noguera, Luis Baldez, Narcis Simon, Lluis A...
153
Voted
DAC
2006
ACM
16 years 1 months ago
Prototyping a fault-tolerant multiprocessor SoC with run-time fault recovery
Modern integrated circuits (ICs) are becoming increasingly complex. The complexity makes it difficult to design, manufacture and integrate these high-performance ICs. The advent o...
Xinping Zhu, Wei Qin
98
Voted
PPDP
2009
Springer
15 years 7 months ago
A declarative encoding of telecommunications feature subscription in SAT
This paper describes the encoding of a telecommunications feature subscription configuration problem to propositional logic and its solution using a state-of-the-art Boolean sati...
Michael Codish, Samir Genaim, Peter J. Stuckey
110
Voted
TCAD
2008
114views more  TCAD 2008»
15 years 12 days ago
Word-Level Predicate-Abstraction and Refinement Techniques for Verifying RTL Verilog
el Predicate Abstraction and Refinement Techniques for Verifying RTL Verilog Himanshu Jain, Daniel Kroening, Natasha Sharygina, and Edmund M. Clarke, Fellow, IEEE As a first step, ...
Himanshu Jain, Daniel Kroening, Natasha Sharygina,...