259 search results - page 9 / 52 » Using Transformations and Verification in Circuit Design |
88
Voted
ASPDAC
2010
ACM
14 years 10 months ago
2010
ACM
Level-sensitive transparent latches are widely used in high-performance sequential circuit designs. Under process variations, the timing of a transparently latched circuit will ada...
ISQED
2003
IEEE
15 years 5 months ago
2003
IEEE
This paper describes the use of integer equations for high level modeling digital circuits for application of formal verification properties at this level. Most formal verificatio...
117
Voted
DATE
2005
IEEE
15 years 6 months ago
2005
IEEE
We present a complete top-down design of a low-power multi-channel clock recovery circuit based on gated current-controlled oscillators. The flow includes several tools and method...
115
Voted
ICCD
2000
IEEE
15 years 4 months ago
2000
IEEE
A major obstacle to widespread acceptance of formal verification is the difficulty in using the tools effectively. Although learning the basic syntax and operation of a formal ver...
112
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IOLTS
2008
IEEE
15 years 6 months ago
2008
IEEE
Present and future semiconductor technologies are characterized by increasing parameters variations as well as an increasing susceptibility to external disturbances. Transient err...