38 search results - page 6 / 8 » Using Tweaks to Design Fault Resistant Ciphers |
DFT
2000
IEEE
15 years 2 months ago
2000
IEEE
Because domino logic design offers smaller area and higher speed than complementary CMOS design, it has been very popularly used to design highperformance processors. However: dom...
DATE
2009
IEEE
15 years 4 months ago
2009
IEEE
Abstract—Multiple-voltage is an effective dynamic power reduction design technique. Recent research has shown that testing for resistive bridging faults in such designs requires ...
EUROCRYPT
2003
Springer
15 years 2 months ago
2003
Springer
ded abstract of this paper appears in Advances in Cryptology – EUROCRYPT ’03, Lecture Notes in Computer Science Vol. 2656, E. Biham ed., Springer-Verlag, 2003. This is the full...
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ITC
1994
IEEE
15 years 1 months ago
1994
IEEE
Previous approaches to designing random pattern testable circuits use post-synthesis test point insertion to eliminate random pattern resistant (r.p.r.) faults. The approach taken...
GECCO
2003
Springer
15 years 2 months ago
2003
Springer
Abstract. The problem of designing symmetric key cryptography algorithms based upon cellular automata (CAs) is considered. The reliability of the Vernam cipher used in the process ...