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GLVLSI
2010
IEEE
164views VLSI» more  GLVLSI 2010»
15 years 2 months ago
Performance and energy trade-offs analysis of L2 on-chip cache architectures for embedded MPSoCs
On-chip memory organization is one of the most important aspects that can influence the overall system behavior in multiprocessor systems. Following the trend set by high-perform...
Mohamed M. Sabry, Martino Ruggiero, Pablo Garcia D...
CF
2006
ACM
15 years 3 months ago
Exploiting locality to ameliorate packet queue contention and serialization
Packet processing systems maintain high throughput despite relatively high memory latencies by exploiting the coarse-grained parallelism available between packets. In particular, ...
Sailesh Kumar, John Maschmeyer, Patrick Crowley
67
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DSD
2008
IEEE
145views Hardware» more  DSD 2008»
15 years 4 months ago
Formulating MITF for a Multicore Processor with SEU Tolerance
While shrinking geometries of embedded LSI devices is beneficial for portable intelligent systems, it is increasingly susceptible to influences from electrical noise, process vari...
Toshimasa Funaki, Toshinori Sato
LCPC
2007
Springer
15 years 3 months ago
Automatic Communication Performance Debugging in PGAS Languages
Recent studies have shown that programming in a Partition Global Address Space (PGAS) language can be more productive than programming in a message passing model. One reason for th...
Jimmy Su, Katherine A. Yelick
IJCAI
1989
14 years 10 months ago
Experiences Implementing a Parallel ATMS on a Shared-Memory Multiprocessor
The Assumption-Based Truth Maintenance System (ATMS) is an important tool in A I . So far its wider use has been limited due to the enormous computational resources which it requi...
Edward Rothberg, Anoop Gupta