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» Using hardware transactional memory for data race detection
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ARC
2010
Springer
186views Hardware» more  ARC 2010»
15 years 3 months ago
Application-Specific Signatures for Transactional Memory in Soft Processors
As reconfigurable computing hardware and in particular FPGA-based systems-on-chip comprise an increasing number of processor and accelerator cores, supporting sharing and synchroni...
Martin Labrecque, Mark Jeffrey, J. Gregory Steffan
SPAA
2010
ACM
15 years 4 months ago
Implementing and evaluating nested parallel transactions in software transactional memory
Transactional Memory (TM) is a promising technique that simplifies parallel programming for shared-memory applications. To date, most TM systems have been designed to efficientl...
Woongki Baek, Nathan Grasso Bronson, Christos Kozy...
88
Voted
ASPLOS
2006
ACM
15 years 5 months ago
Supporting nested transactional memory in logTM
Nested transactional memory (TM) facilitates software composition by letting one module invoke another without either knowing whether the other uses transactions. Closed nested tr...
Michelle J. Moravan, Jayaram Bobba, Kevin E. Moore...
86
Voted
CCECE
2006
IEEE
15 years 5 months ago
Hardware Edge Detection using an Altera Stratix NIOS2 Development Kit
— Edge detection is a computer vision algorithm that is very processor intensive. It is possible to increase the speed of the algorithm by using hardware parallelism. This paper ...
Jay Kraut
91
Voted
ISCA
1993
IEEE
137views Hardware» more  ISCA 1993»
15 years 3 months ago
Transactional Memory: Architectural Support for Lock-Free Data Structures
A shared data structure is lock-free if its operations do not require mutual exclusion. If one process is interrupted in the middle of an operation, other processes will not be pr...
Maurice Herlihy, J. Eliot B. Moss