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» Using hardware transactional memory for data race detection
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JSA
2008
91views more  JSA 2008»
14 years 11 months ago
Using supplier locality in power-aware interconnects and caches in chip multiprocessors
Conventional snoopy-based chip multiprocessors take an aggressive approach broadcasting snoop requests to all nodes. In addition each node checks all received requests. This appro...
Ehsan Atoofian, Amirali Baniasadi
MICRO
2000
IEEE
80views Hardware» more  MICRO 2000»
15 years 4 months ago
Silent stores for free
Silent store instructions write values that exactly match the values that are already stored at the memory address that is being written. A recent study reveals that significant ...
Kevin M. Lepak, Mikko H. Lipasti
DATE
2007
IEEE
81views Hardware» more  DATE 2007»
15 years 6 months ago
Using the inter- and intra-switch regularity in NoC switch testing
This paper proposes an efficient test methodology to test switches in a Network-on-Chip (NoC) architecture. A switch in an NoC consists of a number of ports and a router. Using th...
Mohammad Hosseinabady, Atefe Dalirsani, Zainalabed...
BMCBI
2011
14 years 3 months ago
Proteinortho: Detection of (Co-)Orthologs in Large-Scale Analysis
Background: Orthology analysis is an important part of data analysis in many areas of bioinformatics such as comparative genomics and molecular phylogenetics. The ever-increasing ...
Marcus Lechner, Sven Findeiß, Lydia Steiner,...
VLSID
2001
IEEE
164views VLSI» more  VLSID 2001»
16 years 13 hour ago
An Efficient Parallel Transparent Bist Method For Multiple Embedded Memory Buffers
In this paper, we propose a new transparent built-in self-test ( TBIST ) method to test multiple embedded memory arrays with various sizes in parallel. First, a new transparent tes...
Der-Cheng Huang, Wen-Ben Jone, Sunil R. Das