173 search results - page 31 / 35 » Using hardware transactional memory for data race detection |
76
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ISCA
2010
IEEE
15 years 2 months ago
2010
IEEE
In this paper, we propose ColorSafe, an architecture that detects and dynamically avoids single- and multi-variable atomicity violation bugs. The key idea is to group related data...
ISCA
2009
IEEE
15 years 4 months ago
2009
IEEE
While microprocessor designers turn to multicore architectures to sustain performance expectations, the dramatic increase in parallelism of such architectures will put substantial...
IPPS
2008
IEEE
15 years 3 months ago
2008
IEEE
This paper describes our early experiences with a preproduction Cray XMT system that implements a scalable shared memory architecture with hardware support for multithreading. Unl...
VALUETOOLS
2006
ACM
15 years 3 months ago
2006
ACM
Cache locality optimization is an efficient way for reducing the idle time of modern processors in waiting for needed data. This kind of optimization can be achieved either on the...
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GLOBECOM
2010
IEEE
14 years 6 months ago
2010
IEEE
Abstract--Today's file sharing networks are creating potential security problems to enterprise networks, i.e., the leakage of confidential documents. In order to prevent such ...