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» Using hardware transactional memory for data race detection
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ISLPED
2003
ACM
115views Hardware» more  ISLPED 2003»
15 years 2 months ago
Reducing energy and delay using efficient victim caches
In this paper, we investigate methods for improving the hit rates in the first level of memory hierarchy. Particularly, we propose victim cache structures to reduce the number of ...
Gokhan Memik, Glenn Reinman, William H. Mangione-S...
68
Voted
ISLPED
2006
ACM
74views Hardware» more  ISLPED 2006»
15 years 3 months ago
Power phase variation in a commercial server workload
Many techniques have been developed for adaptive power management of computing systems. These techniques rely on the presence of varying power phases to detect opportunities for a...
W. L. Bircher, L. K. John
91
Voted
JSA
2006
167views more  JSA 2006»
14 years 9 months ago
Pattern-driven prefetching for multimedia applications on embedded processors
Multimedia applications in general and video processing, such as the MPEG4 Visual stream decoders, in particular are increasingly popular and important workloads for future embedd...
Hassan Sbeyti, Smaïl Niar, Lieven Eeckhout
DSD
2008
IEEE
147views Hardware» more  DSD 2008»
14 years 11 months ago
A Low-Cost Cache Coherence Verification Method for Snooping Systems
Due to modern technology trends such as decreasing feature sizes and lower voltage levels, fault tolerance is becoming increasingly important in computing systems. Shared memory i...
Demid Borodin, Ben H. H. Juurlink
77
Voted
VTS
2005
IEEE
95views Hardware» more  VTS 2005»
15 years 3 months ago
SRAM Retention Testing: Zero Incremental Time Integration with March Algorithms
Testing data retention faults (DRFs), particularly in integrated systems on chip comprised of very large number of various sizes and types of embedded SRAMs is challenging and typ...
Baosheng Wang, Yuejian Wu, Josh Yang, André...