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» Using hardware transactional memory for data race detection
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HPCA
2000
IEEE
15 years 1 months ago
Impact of Chip-Level Integration on Performance of OLTP Workloads
With increasing chip densities, future microprocessor designs have the opportunity to integrate many of the traditional systemlevel modules onto the same chip as the processor. So...
Luiz André Barroso, Kourosh Gharachorloo, A...
TPCTC
2010
Springer
147views Hardware» more  TPCTC 2010»
14 years 4 months ago
Assessing and Optimizing Microarchitectural Performance of Event Processing Systems
Abstract. Event Processing (EP) systems are being progressively used in business critical applications in domains such as algorithmic trading, supply chain management, production m...
Marcelo R. N. Mendes, Pedro Bizarro, Paulo Marques
124
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HPCA
2007
IEEE
15 years 3 months ago
An Adaptive Cache Coherence Protocol Optimized for Producer-Consumer Sharing
Shared memory multiprocessors play an increasingly important role in enterprise and scientific computing facilities. Remote misses limit the performance of shared memory applicat...
Liqun Cheng, John B. Carter, Donglai Dai
CASES
2005
ACM
14 years 11 months ago
SECA: security-enhanced communication architecture
In this work, we propose and investigate the idea of enhancing a System-on-Chip (SoC) communication architecture (the fabric that integrates system components and carries the comm...
Joel Coburn, Srivaths Ravi, Anand Raghunathan, Sri...
DATE
2007
IEEE
92views Hardware» more  DATE 2007»
15 years 3 months ago
Test quality analysis and improvement for an embedded asynchronous FIFO
Embedded First-In First-Out (FIFO) memories are increasingly used in many IC designs. We have created a new full-custom embedded FIFO module with asynchronous read and write clock...
Tobias Dubois, Erik Jan Marinissen, Mohamed Aziman...