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» Using hardware transactional memory for data race detection
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ISCA
2007
IEEE
149views Hardware» more  ISCA 2007»
15 years 3 months ago
An effective hybrid transactional memory system with strong isolation guarantees
We propose signature-accelerated transactional memory (SigTM), a hybrid TM system that reduces the overhead of software transactions. SigTM uses hardware signatures to track the r...
Chi Cao Minh, Martin Trautmann, JaeWoong Chung, Au...
IEEEPACT
2008
IEEE
15 years 3 months ago
Scalable and reliable communication for hardware transactional memory
In a hardware transactional memory system with lazy versioning and lazy conflict detection, the process of transaction commit can emerge as a bottleneck. This is especially true ...
Seth H. Pugsley, Manu Awasthi, Niti Madan, Naveen ...
CCGRID
2007
IEEE
15 years 3 months ago
Revisit of View-Oriented Parallel Programming
Traditional parallel programming styles have many problems which hinder the development of parallel applications. The message passing style can be too complex for many programmers...
Z. Huang, W. Chen
ASPLOS
2011
ACM
14 years 1 months ago
Hardware acceleration of transactional memory on commodity systems
The adoption of transactional memory is hindered by the high overhead of software transactional memory and the intrusive design changes required by previously proposed TM hardware...
Jared Casper, Tayo Oguntebi, Sungpack Hong, Nathan...
PLDI
2012
ACM
12 years 12 months ago
Scalable and precise dynamic datarace detection for structured parallelism
Existing dynamic race detectors suffer from at least one of the following three limitations: (i) space overhead per memory location grows linearly with the number of parallel thre...
Raghavan Raman, Jisheng Zhao, Vivek Sarkar, Martin...