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» Using hardware vulnerability factors to enhance AVF analysis
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ISCA
2007
IEEE
130views Hardware» more  ISCA 2007»
14 years 17 days ago
Dynamic prediction of architectural vulnerability from microarchitectural state
Transient faults due to particle strikes are a key challenge in microprocessor design. Driven by exponentially increasing transistor counts, per-chip faults are a growing burden. ...
Kristen R. Walcott, Greg Humphreys, Sudhanva Gurum...
ISCA
2008
IEEE
132views Hardware» more  ISCA 2008»
14 years 20 days ago
Online Estimation of Architectural Vulnerability Factor for Soft Errors
As CMOS technology scales and more transistors are packed on to the same chip, soft error reliability has become an increasingly important design issue for processors. Prior resea...
Xiaodong Li, Sarita V. Adve, Pradip Bose, Jude A. ...
DATE
2010
IEEE
165views Hardware» more  DATE 2010»
13 years 11 months ago
Multicore soft error rate stabilization using adaptive dual modular redundancy
— The use of dynamic voltage and frequency scaling (DVFS) in contemporary multicores provides significant protection from unpredictable thermal events. A side effect of DVFS can ...
Ramakrishna Vadlamani, Jia Zhao, Wayne P. Burleson...
DSN
2007
IEEE
14 years 18 days ago
Architecture-Level Soft Error Analysis: Examining the Limits of Common Assumptions
This paper concerns the validity of a widely used method for estimating the architecture-level mean time to failure (MTTF) due to soft errors. The method first calculates the fai...
Xiaodong Li, Sarita V. Adve, Pradip Bose, Jude A. ...
SIGMETRICS
2006
ACM
116views Hardware» more  SIGMETRICS 2006»
14 years 7 days ago
Applying architectural vulnerability Analysis to hard faults in the microprocessor
In this paper, we present a new metric, Hard-Fault Architectural Vulnerability Factor (H-AVF), to allow designers to more effectively compare alternate hard-fault tolerance scheme...
Fred A. Bower, Derek Hower, Mahmut Yilmaz, Daniel ...