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» Using shared arrays in message-driven parallel programs
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112
Voted
IPPS
2006
IEEE
15 years 6 months ago
Reducing the associativity and size of step caches in CRCW operation
Step caches are caches in which data entered to an cache array is kept valid only until the end of ongoing step of execution. Together with an advanced pipelined multithreaded arc...
M. Forsell
108
Voted
IPPS
2006
IEEE
15 years 6 months ago
Monitoring remotely executing shared memory programs in software DSMs
Peer-to-Peer (P2P) cycle sharing over the Internet has become increasingly popular as a way to share idle cycles. A fundamental problem faced by P2P cycle sharing systems is how t...
Long Fei, Xing Fang, Y. Charlie Hu, Samuel P. Midk...
PLDI
2009
ACM
15 years 7 months ago
Parallelizing sequential applications on commodity hardware using a low-cost software transactional memory
Multicore designs have emerged as the mainstream design paradigm for the microprocessor industry. Unfortunately, providing multiple cores does not directly translate into performa...
Mojtaba Mehrara, Jeff Hao, Po-Chun Hsu, Scott A. M...
98
Voted
IEEEPACT
2006
IEEE
15 years 6 months ago
Region array SSA
Static Single Assignment (SSA) has become the intermediate program representation of choice in most modern compilers because it enables efficient data flow analysis of scalars an...
Silvius Rus, Guobin He, Christophe Alias, Lawrence...
PADS
1996
ACM
15 years 4 months ago
Conservative Circuit Simulation on Shared-Memory Multiprocessors
We investigate conservative parallel discrete event simulations for logical circuits on shared-memory multiprocessors. For a first estimation of the possible speedup, we extend th...
Jörg Keller, Thomas Rauber, Bernd Rederlechne...