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TVLSI
2008
187views more  TVLSI 2008»
15 years 1 months ago
A Design Flow for Architecture Exploration and Implementation of Partially Reconfigurable Processors
During the last years, the growing application complexity, design, and mask costs have compelled embedded system designers to increasingly consider partially reconfigurable applica...
Kingshuk Karuri, Anupam Chattopadhyay, Xiaolin Che...
ISCA
2006
IEEE
125views Hardware» more  ISCA 2006»
15 years 7 months ago
Architectural Semantics for Practical Transactional Memory
Transactional Memory (TM) simplifies parallel programming by allowing for parallel execution of atomic tasks. Thus far, TM systems have focused on implementing transactional stat...
Austen McDonald, JaeWoong Chung, Brian D. Carlstro...
FCCM
2009
IEEE
165views VLSI» more  FCCM 2009»
15 years 8 months ago
Accelerating Quadrature Methods for Option Valuation
This paper presents an architecture for FPGA acceleration of quadrature methods used for pricing complex options, such as discrete barrier, Bermudan, and American options. The arc...
Anson H. T. Tse, David B. Thomas, Wayne Luk
WSC
2007
15 years 4 months ago
Supporting parametrization of business games for multiple educational settings
The parametrization of business games benefits from the usage of a multi-tier architecture and software services. This paper shows that the multi-tier concept supports parametriz...
Stijn-Pieter A. van Houten, Alexander Verbraeck
IWPC
2009
IEEE
15 years 8 months ago
A plethora of paths
A common static software bug detection technique is to use path simulation. Each execution path is simulated using symbolic variables to determine if any software errors could occ...
Eric Larson