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VLSID
2004
IEEE
139views VLSI» more  VLSID 2004»
16 years 2 months ago
Open Defects Detection within 6T SRAM Cells using a No Write Recovery Test Mode
The detection of all open defects within 6T SRAM cells is always a challenge due to the significant test time requirements. This paper proposes a new design-for-test (DFT) techniq...
André Ivanov, Baosheng Wang, Josh Yang
ESTIMEDIA
2003
Springer
15 years 7 months ago
EPIC-Explorer: A Parameterized VLIW-based Platform Framework for Design Space Exploration
— The constant increase in levels of integration and the reduction of the time-to-market have led to the definition of new methodologies stressing reuse. This involves not only ...
Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi,...
TC
2010
14 years 8 months ago
FPGA Designs with Optimized Logarithmic Arithmetic
Using a general polynomial approximation approach, we present an arithmetic library generator for the logarithmic number system (LNS). The generator produces optimized LNS arithmet...
Haohuan Fu, Oskar Mencer, Wayne Luk
IJCCBS
2010
146views more  IJCCBS 2010»
15 years 6 days ago
A meta-level true random number generator
: True random number generators (TRNGs) are extensively used in cryptography, simulations and statistics. In this work, we introduce, extend and analyse the concept of the randomis...
Bernhard Fechner, Andre Osterloh
CASES
2006
ACM
15 years 7 months ago
FlashCache: a NAND flash memory file cache for low power web servers
We propose an architecture that uses NAND flash memory to reduce main memory power in web server platforms. Our architecture uses a two level file buffer cache composed of a re...
Taeho Kgil, Trevor N. Mudge