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TVLSI
2008
164views more  TVLSI 2008»
15 years 4 months ago
Dynamically Configurable Bus Topologies for High-Performance On-Chip Communication
The on-chip communication architecture is a major determinant of overall performance in complex System-on-Chip (SoC) designs. Since the communication requirements of SoC components...
Krishna Sekar, Kanishka Lahiri, Anand Raghunathan,...
TVLSI
2008
157views more  TVLSI 2008»
15 years 4 months ago
Scalable QoS-Aware Memory Controller for High-Bandwidth Packet Memory
This paper proposes a high-performance scalable quality-of-service (QoS)-aware memory controller for the packet memory where packet data are stored in network routers. A major chal...
Hyuk-Jun Lee, Eui-Young Chung
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TVLSI
2008
126views more  TVLSI 2008»
15 years 4 months ago
Body Bias Voltage Computations for Process and Temperature Compensation
With continued scaling into the sub-90nm regime, the role of process, voltage and temperature (PVT) variations on the performance of VLSI circuits has become extremely important. T...
Sanjay V. Kumar, Chris H. Kim, Sachin S. Sapatneka...
AMC
2004
108views more  AMC 2004»
15 years 4 months ago
A variational approach to magnetic resonance coil sensitivity estimation
Abstract. A variational method for estimating a magnetic resonance coil sensitivity from its corresponding nonuniform illumination of magnetic resonance images is proposed and anal...
Stephen L. Keeling, Roland Bammer
TVLSI
2008
187views more  TVLSI 2008»
15 years 4 months ago
A Design Flow for Architecture Exploration and Implementation of Partially Reconfigurable Processors
During the last years, the growing application complexity, design, and mask costs have compelled embedded system designers to increasingly consider partially reconfigurable applica...
Kingshuk Karuri, Anupam Chattopadhyay, Xiaolin Che...
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