285 search results - page 25 / 57 » Using the Compiler to Improve Cache Replacement Decisions |
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ISPDC
2010
IEEE
14 years 8 months ago
2010
IEEE
—Super-scalar, out-of-order processors that can have tens of read and write requests in the execution window place significant demands on Memory Level Parallelism (MLP). Multi- ...
LCTRTS
2007
Springer
15 years 3 months ago
2007
Springer
The Instruction Register File (IRF) is an architectural extension for providing improved access to frequently occurring instructions. An optimizing compiler can exploit an IRF by ...
SIGARCH
2008
14 years 9 months ago
2008
1 This paper presents a simple but effective method to reduce on-chip access latency and improve core isolation in CMP Non-Uniform Cache Architectures (NUCA). The paper introduces ...
ICCAD
2008
IEEE
15 years 6 months ago
2008
IEEE
— Leveraging the power of scratchpad memories (SPMs) available in most embedded systems today is crucial to extract maximum performance from application programs. While regular a...
INFOCOM
2007
IEEE
15 years 3 months ago
2007
IEEE
— In many networked applications, independent caching agents cooperate by servicing each other’s miss streams, without revealing the operational details of the caching mechanis...